The present invention relates to a technology which is effective when applied to a device formation technique in a semiconductor device (or semiconductor integrated circuit device) and a manufacturing method thereof, i.e., particularly in a normally-off power JEFT and a manufacturing method thereof.
Japanese Unexamined Patent Publication No. 2008-66619 (Patent Document 1) discloses a Multi-Epitaxy technique in which, as a manufacturing process of a Normally-ON JFET (Junction Field Effect Transistor), epitaxial growth and ion implantation into portions serving as gates are repeated several times, and then activation annealing is simultaneously performed.